Over the last several years, the use of fiber optics for transmissions of telephony signals has gained wider acceptance in the telecommunication field. In particular, the synchronous optical network standard known as SONET has developed appreciable usage. The SONET format requires that telephony signals operating in different formats, such as DS-1 signals, DS-2 signals, DS-3 signals, and fiber distributed data interface (FDDI), need to be desynchronized from their SONET format or other formats associated with telephony transmission. In particular, such desynchronizers must meet specifications with regard to phase jumps caused by pointer changes such as a DS-1 signal being mapped into a SONET virtual tributary (VT) such as a VT 1.5 payload.
To accomplish such a result, there is a need for very low bandwidth phase lock loops in order to smooth the phase jumps associated with such pointer changes. An approach for implementing such smooth phase jumps could be based upon analog loop circuitry, which for the particular implementation noted above, could be used to reduce the eight Unit Interval (UI) pointer adjustment in order to extract a DS-1 payload from a SONET VT 1.5 payload. In order to accomplish this result with analog circuitry, bandwidths in the 2 Hz region are required to reduce the jitter content of the output phase transition to levels approximately equal to 1.5 UI, with lower jitter levels being more desirable, but of course requiring lower bandwidths. Bandwidths this low require extremely large time constants (time constant .tau.=rc) and therefore large component values for the filter resistor and capacitor. In addition, such analog phase lock loops are slow to lock, thus causing large time delays after transients have occurred before the DS-1 channel can be used for data transmission again.
Another approach for coping with such pointer changes is to use a fixed bit leak-out desynchronizer. For DS-1 format desynchronizers using this technique, it is possible to use relatively large bandwidths analog phase lock loops operating in the 50 to 400 Hz range which are adequate to filter waiting time and mapping jitter. However, such a desynchronizer still requires a digital adjunct circuit to hide low occurrence transient effects such as pointer adjustments from the high bandwidth analog phase lock loop. If these transients are not hidden from the high bandwidth phase lock loop, jitter approaching 8 UI pp can occur from a single VT pointer adjustment.
While such a fixed bit leak desynchronizer hides the bulk of the pointer movement from the high bandwidth phase lock loop, it performs equalization by leaking out the original pointer adjustment one bit at a time, into a high bandwidth phase lock loop. Such an equalization is necessary in order to prevent the desynchronizer's elastic store from overflowing. Thus, as each bit is leaked out, usually as fast as possible without exceeding the overall payload output jitter specification, jitter from 0.7 to 1.5 UI pp is generated by the phase transitions in the output signal.
The present invention overcomes the above-mentioned difficulties by effectively hiding pointer adjustments as noted above through use of a technique configured as an inline piece-wise linear adaptive leaking architecture. This architecture employs a digital elastic store position detection circuit, a digital frame induced jitter filtering circuit, a digital leak rate filter circuit, and a digital frequency synthesizer (VCO). The magnitude of the jitter can be reduced to any arbitrarily low level by adjusting the digital VCO gain characteristics and the digital rate filter integration time constant, and hence, the bandwidth.
The present invention has the same net effect as the analog only phase lock loop described above, except that very low analog phase lock loop bandwidths are not required. The embodiment of the present invention uses very low bandwidth characteristics to produce a digitally synthesized output clock which is coupled to a commercially available analog/digital phase lock loop circuit. The commercially available phase lock loop has an effective bandwidth of 6 Hz and is required only for smoothing the high frequency jitter in the synthesized output clock and providing a line interface function.